1. Field of the Invention
The present invention is generally in the field of circuit design. More specifically, the present invention is in the field of designing circuits including at least one MOSFET.
2. Background Art
The demand for advanced consumer electronic devices, such as cellular phones and other wireless devices, has challenged semiconductor manufacturers to reduce the time-to-market for the low-power radio frequency integrated circuits (xe2x80x9cRFICxe2x80x9d) these products contain. In an effort to meet that challenge, semiconductor manufacturers use automated design systems that provide the designer with sets of tools and methodologies that reduce the entire design cycle of the RFIC.
A typical RFIC design system includes a design cycle that comprises various steps. For example, the steps in an RFIC design cycle can include circuit design and simulation, circuit layout generation, circuit layout verification, and extraction of parasitics from the circuit layout. The initial circuit design and simulation is performed before the designer has knowledge of the exact layout of the entire circuit, which is generated later in the design cycle. As a result, the designer has to attempt to predict and counteract the effect of various parasitics that might be introduced during layout design, which can severely degrade circuit performance.
Timing, voltage levels, and race conditions have to be re-verified after the designer knows of exact parasitics, such as parasitic capacitance, resistance, and inductance, extracted from circuit layout. Thus, a new circuit simulation incorporating correct values of the extracted parasitics from the circuit layout is required. Even then, the new circuit layout will often result in different values of extracted parasitics. Some parasitics may be eliminated, some new ones may be introduced, and some may increase or decrease, as such resulting in the need to redesign and re-simulate the circuit. The above steps are repeated, where the circuit design is modified by re-extracted parasitics from the circuit layout.
Without precise knowledge of the effect circuit modifications have on parasitics extracted from the circuit layout, the designer has to continually attempt to predict what new parasitics might be generated from the latest circuit modifications. Thus, the circuit""s design cycle continues through numerous, time consuming iterations until the circuit layout parasitics have been correctly taken into account during the circuit design and simulation cycle. This repetitious cycle can result in many days or weeks of delay in completion of the circuit design for large circuit blocks. The resulting increase in xe2x80x9ctime-to-marketxe2x80x9d causes a tremendous economic loss to semiconductor design houses and manufacturers.
FIG. 1 shows flowchart 100, which illustrates a typical sequence of steps in a circuit""s design, layout, and verification. In step 102 in FIG. 1, a circuit is designed and a schematic for the circuit is made. The circuit is also simulated in step 102. The circuit can be designed with the assistance of a commercial circuit design editor, such as Composer(copyright), by Cadence Design Systems(copyright), Inc. For example, a circuit comprising a number of RF MOSFETs can be input in the circuit schematic. As a part of the circuit design and schematic formation, parameters such as xe2x80x9cfinger widthxe2x80x9d (xe2x80x9cWFxe2x80x9d), xe2x80x9cfinger lengthxe2x80x9d (xe2x80x9cLFxe2x80x9d), and xe2x80x9cnumber of fingersxe2x80x9d (xe2x80x9cNFxe2x80x9d) can be input in the circuit design editor and into the schematic. Thus, for example, the resulting circuit schematic would comprise symbols corresponding to the RF MOSFET, together with the above-mentioned parameters, i.e. WF, LF, and NF.
A simulation program can simulate the electrical behavior of a circuit using the parameters that were input for the circuit""s components. For example, the simulation program can predict the electrical behavior of RF MOSFETs mentioned above using the input parameters WF, LF, and NF. However, the accuracy of the results obtained from the circuit simulation depend on the accuracy of all the circuit components, including a large number of parasitic components, whose values cannot generally be accurately estimated by conventional design techniques. The circuit simulation can be written and performed, for example, by using the SPICE(copyright) program.
In step 104, a circuit layout is generated in a layout generator. For example, the layout generator can interpret the WF, LF, and NF parameters of the RF MOSFETs that were input with the RF MOSFET""s symbol in the circuit""s schematic in step 102, and generate an RF MOSFET layout. The layout generator program can be written in SKILL(copyright), C++, a combination of the two languages, or a combination of a number of other languages.
In step 106 in FIG. 1, a design rule check (xe2x80x9cDRCxe2x80x9d) and a layout versus circuit schematic (xe2x80x9cLVSxe2x80x9d) verification is performed on the circuit layout generated in step 104. DRC is performed to ensure that the circuit layout conforms to all manufacturing specifications. For example, the DRC program identifies problems such as xe2x80x9cminimum-spacingxe2x80x9d violations and xe2x80x9cminimum-widthxe2x80x9d violations. In LVS, the circuit layout is checked against the circuit schematic to ensure electrical equivalence. In other words, the circuit layout is checked to see that it corresponds to the circuit schematic. By way of example, the LVS checking can be implemented using the Calibre(copyright) program and a rule file written in Calibre(copyright) format.
In step 108, parasitics are extracted from the circuit layout. For example, in an RF MOSFET layout, both the RF MOSFET""s xe2x80x9cinternalxe2x80x9d parasitics, and the parasitics generated by the interconnect routing between the RF MOSFET and other circuit components, are extracted. For example, the RF MOSFET""s internal parasitics can include, among other things, the capacitance between the RF MOSFET""s source and the xe2x80x9cbulkxe2x80x9d (i.e. the silicon substrate), and the resistance between the RF MOSFET""s source and the xe2x80x9cbulk.xe2x80x9d
It is noted that the RF MOSFET""s internal parasitics have a great effect on circuit performance. The internal and interconnect routing parasitics are used by the circuit designer to modify the circuit schematic in step 102, and the circuit design cycle comprising steps 102, 104, 106, and 108 begins anew. A modified circuit layout is generated in step 104, and DRC and LVS are performed on the modified circuit layout in step 106. In step 108, parasitics are extracted from the modified circuit layout. For example, for the circuit comprising the RF MOSFET discussed above, both the RF MOSFET""s xe2x80x9cinternalxe2x80x9d parasitics, and the parasitics generated by the interconnect routing between the RF MOSFET and other circuit components, would again be extracted. Thus, the circuit design cycle comprising steps 102, 104, 106, and 108 as discussed above is repeated until circuit design and simulation step 102 can be performed with a high degree of confidence in the parasitic values that correspond to the circuit layout. As discussed above, the repetitive circuit design cycle significantly increases the time-to-market for integrated circuits such as RFICs.
Therefore, there exists a need for an integrated design system that provides a reduction in the time-to-market for integrated circuits, such as RFICs comprising RF MOSFETs. More specifically, there exists a need for an integrated design system that is able to predict the parasitics that will result from an RF MOSFET layout before the layout is generated, and thereby minimize undesirable repetition of the circuit design cycle.
The present invention is directed to method and system for predictive MOSFET layout generation with reduced design cycle. The invention provides a reduction in the time-to-market for integrated circuits, such as RFICs comprising RF MOSFETs. More specifically, the invention is an integrated design system that is able to predict the parasitics that will result from an RF MOSFET layout before the layout is generated, thereby minimizing undesirable repetitions in the circuit design cycle.
In one embodiment, the invention receives a number of parameter values for an RF MOSFET. Examples of parameter values are style, bulk contact, finger width, finger length, number of fingers, current, and slice parameter values. From the received parameter values, a number of parasitic values for a subcircuit model of the RF MOSFET are determined. For example, parasitic resistor values and parasitic capacitor values of the RF MOSFET are determined.
The parasitic resistor values and parasitic capacitor values are used in simulating the circuit comprising the RF MOSFET. According to the present invention, an RF MOSFET layout is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the circuit comprising the RF MOSFET. As such, the parasitic values of the RF MOSFET have already been taken into account in the initial circuit simulation and there is no need to extract the internal parasitics of the RF MOSFET for further circuit simulations.